Due to the high integration density of electronic circuits and storages, the frequency of errors increases.
Apart from 1-Bit-errors, increasingly also 2-Bit-errors and general multi-bit errors are to be considered, i.e. to be corrected and to be detected. In particular, in error correction it is important to correct the occurred errors quickly, if possible within the current clock cycle in order to prevent a delayed processing of the corrected data as compared to the uncorrected data.
Frequently, data are written into a storage under an address and read out after some time. Here it is possible that the data when read out of the storage are faulty or corrupt and have to be corrected after reading it out.
Here, both one bit errors, two bit errors and generally multi-bit errors occur, which are caused randomly with decreasing probability, and also errors occur in which all memory cells take on the value 0 erroneously, which is to be referred to as “All-0”, and also errors where all memory cells take on the value 1, to be referred to here as “All-1”.
It is also of special interest to detect possible address errors with a high probability, as a faulty address for example when reading out of a storage, may lead to completely different data. It is possible to correct one bit errors by Hamming code or Hsia-codes and 2-Bit-errors relatively fast by BCH-Codes implemented in parallel.
Disadvantageous with prior solutions for 1-bit and 2-bit error correction is, for example, that the errors “All-0” and “All-1” are not part of error detection. Generally, it is of high interest to improve the reliability of error correction and error detection concepts.